1. Field of the Invention
The present invention relates to a memory system and a control method therefor, and more particularly relates to a memory system having a configuration in which a plurality of memory devices are commonly connected to a memory controller and a control method for the memory system.
2. Description of Related Art
In a memory system including a memory device such as a DRAM (Dynamic Random Access Memory), there are cases that a plurality of memory devices are commonly connected to a memory controller so as to increase the memory capacity of the entire system. The memory controller is a control device that issues various commands such as a read command and a write command to the memory devices, as well as receiving read data and transmitting write data. The memory controller is mainly provided between a CPU (Central Processing Unit) and memory devices, but occasionally the CPU itself functions as the memory controller.
As described above, in the case of a memory system in which a plurality of memory devices are commonly connected to a memory controller, there is a variation in a time taken from when the memory controller issues a read command until when each of the memory devices receives read data. This variation is caused by various factors such as that caused by a manufacturing process or that caused by a wiring load. A variation caused by a wiring load is cancelled in almost all cases in a memory system in which memory devices are stacked, for example. However, the variation caused by a manufacturing process cannot be cancelled in the memory system, and this variation appears as a time difference that is not negligible.
When there is a variation in a delay time from when the memory controller issues a read command until when each of the memory devices receives read data, a latch margin of read data at a memory controller side decreases. For example, when a memory device with a long delay time and a memory device with a short delay time are continuously accessed, read data from the memory device with the long delay time and read data from the memory device with the short delay time are partially duplicated with each other. Therefore, an effective width (a pass window) of these read data becomes narrower. Furthermore, there is another problem that, when logic levels of the read data from the memory device with the long delay time and the read data from the memory device with the short delay time which are continuously read out are different, a through current flows during a duplicating period of the read data.
Japanese Patent No. 3558599 proposes a method of preventing such a problem of a variation in delay times.
However, according to the method described in Japanese Patent No. 3558599, because adjustment of delay times is performed corresponding to a delay time that is monitored as needed, the adjustment may not be able to catch up with the data transmission when it is a considerably high speed. Therefore, there has been demanded a method that is capable of reliably cancelling a variation in delay time even when data is transmitted at a considerably high speed.